The advent of Ultra Large Scale Integration (ULSI) circuit technologies has concurrently prompted reductions in the dimensions of semiconductor devices. To accommodate ULSI applications, the size of various devices, including memory cells, as well as the area available therefor on integrated circuits, has been significantly decreased. In particular, the area for forming a dynamic random access memory cell has been reduced to dimensions in the submicron range, thus achieving higher chip density. The dimensions of semiconductor devices will continue to decrease.
Integrated circuit fabrication involves the formation of semiconductor devices, isolation structure, electrical connection and passivation. Passivation is typically used, among other purposes, to prevent moisture from penetrating into underlying layers of semiconductor devices. Conventional passivation techniques involve forming a protective layer over semiconductor devices. One such layer used to perform passivation is a silicon oxide/silicon nitride composition (oxide/nitride) layer. The oxide/nitride layer is typically deposited by plasma enhanced chemical vapor deposition (PECVD).
The reduction in semiconductor devices has created problems in passivation. More specifically, as device dimensions are reduced, so are spacings between metal lines. The reduction in spacing between metal lines in turn complicates and, in some circumstances, altogether prevents effective passivation. FIGS. 1 and 2 illustrate a semiconductor substrate 2 having an isolation layer 4. An oxide/nitride layer 8 is formed on a metal layer 6. The oxide/nitride layer 8 is intended to function as a passivation layer.
However, as shown in FIG. 1, the close proximity between metal regions, i.e., density, of the metal layer 6 undesirably causes the formation of key holes 10 in the oxide/nitride layer 8. The presence of key holes 10 traps photoresist and results in the blowout of photoresist during photoresist stripping. These consequences associated with the presence of key holes 10 cause bond pad corrosion and also degrade reliability.
The PECVD oxide/nitride layer used in conventional passivation techniques have other disadvantages. One significant disadvantage is poor step coverage, as shown in FIG. 2. It will be appreciated that poor step coverage causes failures in pin hole testing and pressure cook testing.
What is required is a new and improved passivation process to overcome the aforementioned disadvantages associated with conventional passivation techniques.